The phenomenon of electrostatic discharge (ESD) gives rise to images of lightning strikes or the sparks that leap from one’s fingertips when touching a doorknob in dry winter. The sparks are the result of the ionization of the air gap between the charged human body and the zero-potential surface of the doorknob. Clearly a high voltage discharge takes place under these circumstances with highly visible (and sometimes tangible) effects. In the semiconductor industry, the potentially destructive nature of ESD in integrated circuits (IC) became more apparent as semiconductor devices became smaller and more complex. The high voltages result in large electric fields and high current densities in the small devices, which can lead to breakdown of insulators and thermal damage in the IC.
The losses in the IC industry caused by ESD can be substantial if no efforts are made to understand and solve the problem [Wagner93]. Figure 1.1 shows that the distribution of failure modes observed in silicon ICs and ESD is observed to account for close to 10% of all failures [Green88]. The largest category is that of electrical overstress (EOS), of which ESD is a subset. In many cases, failures classified as EOS could actually be due to ESD, which would make this percentage even higher [Merrill93].
The significance of ESD as an IC failure mode has led to concerted efforts by IC manufacturers and university research workers in the US, Europe, and Japan to study the phenomena. Progress has been made in understanding the different types of ESD events affecting ICs, which has enabled test methods to be developed to characterize their ESD [Bhar83][Greason87]. ESD prevention programs have been put in place during IC manufacturing, testing, and handling, which have reduced the buildup of static and the exposure of ICs to ESD. Studies have been made of the nature of destruction in IC chips and, based on this work, techniques for designing protection circuits have been implemented, which has made it possible for the present generation of complex ICs to be robust for ESD.
The introduction of each new generation of silicon technology results in new challenges in terms of ESD capability and protection circuit design.
Initially the ESD performance improves as the circuit designs mature and problems are solved or debugged. After a certain time the technology changes (i.e., LDD, silicides) cause the circuit to no longer function to its original capability, and the introduction of new protection techniques are needed to restore good ESD performance. CMOS ICs in automotive environments require very high ESD protection levels, which places an even higher demand on the design of protection circuits. The speed with which new technologies are introduced have reduced available time for protection circuit development. In fact it is becoming more and more important to design circuits that can be transferred into the newer technologies with minimum changes. Hence, it is necessary to understand the main issues involved in ESD protection circuit design and the physical mechanisms taking place in order to ensure that the design can be scaled or transferred with minimum impact to the ESD performance.
The importance of building-in reliability demands design approaches that include ESD robustness as part of the technology roadmap.
The design and optimization of circuits with ultrasmall transistors (sub-0.25 µm) use a large number of simulation tools prior to committing the circuits to silicon.
Thus, modeling and simulation of ESD effects in the protection circuit is important;
we discuss the main approaches here. The book is aimed at providing an overall
picture of the issues involved in ESD protection circuit design and analysis. It is
intended to provide a basis in this field for circuit design and reliability engineers
as well as process and device design engineers who have to deal with ESD in
integrated circuits.
The losses in the IC industry caused by ESD can be substantial if no efforts are made to understand and solve the problem [Wagner93]. Figure 1.1 shows that the distribution of failure modes observed in silicon ICs and ESD is observed to account for close to 10% of all failures [Green88]. The largest category is that of electrical overstress (EOS), of which ESD is a subset. In many cases, failures classified as EOS could actually be due to ESD, which would make this percentage even higher [Merrill93].
The significance of ESD as an IC failure mode has led to concerted efforts by IC manufacturers and university research workers in the US, Europe, and Japan to study the phenomena. Progress has been made in understanding the different types of ESD events affecting ICs, which has enabled test methods to be developed to characterize their ESD [Bhar83][Greason87]. ESD prevention programs have been put in place during IC manufacturing, testing, and handling, which have reduced the buildup of static and the exposure of ICs to ESD. Studies have been made of the nature of destruction in IC chips and, based on this work, techniques for designing protection circuits have been implemented, which has made it possible for the present generation of complex ICs to be robust for ESD.
The introduction of each new generation of silicon technology results in new challenges in terms of ESD capability and protection circuit design.
Initially the ESD performance improves as the circuit designs mature and problems are solved or debugged. After a certain time the technology changes (i.e., LDD, silicides) cause the circuit to no longer function to its original capability, and the introduction of new protection techniques are needed to restore good ESD performance. CMOS ICs in automotive environments require very high ESD protection levels, which places an even higher demand on the design of protection circuits. The speed with which new technologies are introduced have reduced available time for protection circuit development. In fact it is becoming more and more important to design circuits that can be transferred into the newer technologies with minimum changes. Hence, it is necessary to understand the main issues involved in ESD protection circuit design and the physical mechanisms taking place in order to ensure that the design can be scaled or transferred with minimum impact to the ESD performance.
The importance of building-in reliability demands design approaches that include ESD robustness as part of the technology roadmap.
The design and optimization of circuits with ultrasmall transistors (sub-0.25 µm) use a large number of simulation tools prior to committing the circuits to silicon.
Thus, modeling and simulation of ESD effects in the protection circuit is important;
we discuss the main approaches here. The book is aimed at providing an overall
picture of the issues involved in ESD protection circuit design and analysis. It is
intended to provide a basis in this field for circuit design and reliability engineers
as well as process and device design engineers who have to deal with ESD in
integrated circuits.
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